新聞動態
Design tool handles LynxSecure hypervisor on Cortex-A53
New to the tool is the development of virtualised applications for ARM Cortex-A53, by providing hypervisor awareness for Lynx Software Technologies’ LynxSecure hypervisor.
“At present there is a trend to consolidate multiple applications, which in the past used separate hardware, on a single computing platform,” said PLS. “However, different requirements in terms of safety, security and real-time behaviour demand strict isolation, which can only be achieved by virtualisation. With the hypervisor awareness, the developer can now use the debug capabilities of the UDE for the development of virtualized applications too.”
Specific features of the ARM Cortex-A53, such as two-stage address translation or the support of virtual interrupts are handled transparently for the users.
Such hypervisor awareness enables the user to debug a bare-metal application as usual and as if it was running on real hardware instead of being encapsulated within a virtual machine.
If required, UDE also provides support for debugging and system analysis of the hypervisor itself.
For each individual virtual machine, both the state and the contexts can be displayed.
In addition, information about the memory layout of the individual virtual machines, as well as the mapping of the virtual memory addresses to physical memory addresses, is provided.
Handling of large quantities of recorded trace data has been improved in 5.0. For example, time-accurate display of executed functions and operating system tasks can now be sorted and filtered according to different criteria – and links allow navigation from the recorded functions to their source code.
“In combination with the add-in for the support of real-time operating systems according to the OSEK [Open systems and their interfaces for the electronics in motor vehicles] standard, the operating system tasks and associated runnables can be clearly displayed and measured,” claimed PLS.
New processors covered include the 32bit ARM Cortex-R52 and the NETX 90 Cortex-M microcontroller.
“At present there is a trend to consolidate multiple applications, which in the past used separate hardware, on a single computing platform,” said PLS. “However, different requirements in terms of safety, security and real-time behaviour demand strict isolation, which can only be achieved by virtualisation. With the hypervisor awareness, the developer can now use the debug capabilities of the UDE for the development of virtualized applications too.”
Specific features of the ARM Cortex-A53, such as two-stage address translation or the support of virtual interrupts are handled transparently for the users.
Such hypervisor awareness enables the user to debug a bare-metal application as usual and as if it was running on real hardware instead of being encapsulated within a virtual machine.
If required, UDE also provides support for debugging and system analysis of the hypervisor itself.
For each individual virtual machine, both the state and the contexts can be displayed.
In addition, information about the memory layout of the individual virtual machines, as well as the mapping of the virtual memory addresses to physical memory addresses, is provided.
Handling of large quantities of recorded trace data has been improved in 5.0. For example, time-accurate display of executed functions and operating system tasks can now be sorted and filtered according to different criteria – and links allow navigation from the recorded functions to their source code.
“In combination with the add-in for the support of real-time operating systems according to the OSEK [Open systems and their interfaces for the electronics in motor vehicles] standard, the operating system tasks and associated runnables can be clearly displayed and measured,” claimed PLS.
New processors covered include the 32bit ARM Cortex-R52 and the NETX 90 Cortex-M microcontroller.